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semiconductor 3-64 november 1996 ca3130, ca3130a 15mhz, bimos operational ampli?er with mosfet input/cmos output features ? mosfet input stage provides: - very high z i = 1.5 t w (1.5 x 10 12 w ) (typ) - very low i i = 5pa (typ) at 15v operation = 2pa (typ) at 5v operation ? ideal for single-supply applications ? common-mode input-voltage range includes negative supply rail; input terminals can be swung 0.5v below negative supply rail ? cmos output stage permits signal swing to either (or both) supply rails applications ? ground-referenced single supply ampli?ers ? fast sample-hold ampli?ers ? long-duration timers/monostables ? high-input-impedance comparators (ideal interface with digital cmos) ? high-input-impedance wideband ampli?ers ? voltage followers (e.g. follower for single-supply d/a converter) ? voltage regulators (permits control of output voltage down to 0v) ? peak detectors ? single-supply full-wave precision recti?ers ? photo-diode sensor ampli?ers description ca3130a and ca3130 are op amps that combine the advantage of both cmos and bipolar transistors. gate-protected p-channel mosfet (pmos) transistors are used in the input circuit to provide very-high-input impedance, very-low-input current, and exceptional speed performance. the use of pmos transistors in the input stage results in common-mode input-voltage capability down to 0.5v below the negative-supply terminal, an important attribute in single-supply applications. a cmos transistor-pair, capable of swinging the output volt- age to within 10mv of either supply-voltage terminal (at very high values of load impedance), is employed as the output circuit. the ca3130 series circuits operate at supply voltages ranging from 5v to 16v, ( 2.5v to 8v). they can be phase compensated with a single external capacitor, and have ter- minals for adjustment of offset voltage for applications requiring offset-null capability. terminal provisions are also made to permit strobing of the output stage. the ca3130a offers superior input characteristics over those of the ca3130. pinouts ca3131, ca3130a (pdip, soic) top view ca3130, ca3130a (metal can) top view offset inv. non-inv. v- 1 2 3 4 8 7 6 5 strobe v+ output offset - + null input input null tab output inv. v- and case offset non-inv. v + offset 2 4 6 1 3 7 5 8 - + strobe phase compensation null input input null ordering information part no. (brand) temp. range ( o c) package pkg. no. ca3130ae -55 to 125 8 ld pdip e8.3 ca3130am (3130a) -55 to 125 8 ld soic m8.15 ca3130am96 (3130a) -55 to 125 8 ld soic (note) m8.15 ca3130at -55 to 125 8 pin metal can t8.c CA3130BT -55 to 125 8 pin metal can t8.c ca3130e -55 to 125 8 ld pdip e8.3 ca3130m (3130) -55 to 125 8 ld soic m8.15 ca3130m96 (3130) -55 to 125 8 ld soic (note) m8.15 ca3130t -55 to 125 8 pin metal can t8.c note: denotes tape and reel. caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? harris corporation 1996 file number 817.3
3-65 absolute maximum ratings thermal information dc supply voltage (between v+ and v- terminals) . . . . . . . . . 16v differential input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8v dc input voltage . . . . . . . . . . . . . . . . . . . . . . (v+ +8v) to (v- -0.5v) input-terminal current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1ma output short-circuit duration (note 1) . . . . . . . . . . . . . . . . inde?nite operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . -50 o c to 125 o c thermal resistance (typical, note 2) q ja ( o c/w) q jc ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . 100 n/a soic package . . . . . . . . . . . . . . . . . . . 160 n/a metal can package . . . . . . . . . . . . . . . 170 85 maximum junction temperature ( metal can package). . . . . . . 175 o c maximum junction temperature (plastic package) . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. notes: 1. short circuit may be applied to ground or to either supply. 2. q ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?cations t a = 25 o c, v+ = 15v, v- = 0v, unless otherwise speci?ed parameter symbol test conditions ca3130 ca3130a units min typ max min typ max input offset voltage |v io |v s = 7.5v - 8 15 - 2 5 mv input offset voltage temperature drift d v io / d t - 10 - - 10 - m v/ o c input offset current |i io |v s = 7.5v - 0.5 30 - 0.5 20 pa input current i i v s = 7.5v - 5 50 - 5 30 pa large-signal voltage gain a ol v o = 10v p-p r l = 2k w 50 320 - 50 320 - kv/v 94 110 - 94 110 - db common-mode rejection ratio cmrr 70 90 - 80 90 - db common-mode input voltage range v icr 0 -0.5 to 12 10 0 -0.5 to 12 10 v power-supply rejection ratio d v io / d v s v s = 7.5v - 32 320 - 32 150 m v/v maximum output voltage v om +r l = 2k w 12 13.3 - 12 13.3 - v v om -r l = 2k w - 0.002 0.01 - 0.002 0.01 v v om +r l = 14.99 15 - 14.99 15 - v v om -r l = - 0 0.01 - 0 0.01 v maximum output current i om + (source) at v o = 0v 12 22 45 12 22 45 ma i om - (sink) at v o = 15v 12 20 45 12 20 45 ma supply current i+ v o = 7.5v, r l = - 10 15 - 10 15 ma i+ v o = 0v, r l = -23-23ma ca3130, ca3130a
3-66 electrical speci?cations typical values intended only for design guidance, v supply = 7.5v, t a = 25 o c unless otherwise speci?ed parameter symbol test conditions ca3130, ca3130a units input offset voltage adjustment range 10k w across terminals 4 and 5 or 4 and 1 22 mv input resistance r i 1.5 t w input capacitance c i f = 1mhz 4.3 pf equivalent input noise voltage e n bw = 0.2mhz, r s = 1m w (note 3) 23 m v open loop unity gain crossover frequency (for unity gain stability 3 47pf required.) f t c c = 0 15 mhz c c = 47pf 4 mhz slew rate: sr c c = 0 30 v/ m s open loop closed loop c c = 56pf 10 v/ m s transient response: c c = 56pf, c l = 25pf, r l = 2k w (voltage follower) 0.09 m s rise time t r overshoot os 10 % settling time (to <0.1%, v in = 4v p-p )t s 1.2 m s note: 3. although a 1m w source is used for this test, the equivalent input noise remains constant for values of r s up to 10m w. electrical speci?cations typical values intended only for design guidance, v+ = 5v, v- = 0v, t a = 25 o c unless otherwise speci?ed (note 4) parameter symbol test conditions ca3130 ca3130a units input offset voltage v io 82mv input offset current i io 0.1 0.1 pa input current i i 22pa common-mode rejection ratio cmrr 80 90 db large-signal voltage gain a ol v o = 4v p-p , r l = 5k w 100 100 kv/v 100 100 db common-mode input voltage range v icr 0 to 2.8 0 to 2.8 v supply current i+ v o = 5v, r l = 300 300 m a v o = 2.5v, r l = 500 500 m a power supply rejection ratio d v io / d v+ 200 200 m v/v note: 4. operation at 5v is not recommended for temperatures below 25 o c. ca3130, ca3130a
3-67 schematic diagram application information circuit description figure 1 is a block diagram of the ca3130 series cmos operational ampli?ers. the input terminals may be operated down to 0.5v below the negative supply rail, and the output can be swung very close to either supply rail in many applications. consequently, the ca3130 series circuits are ideal for single-supply operation. three class a ampli?er stages, having the individual gain capability and current consumption shown in figure 1, provide the total gain of the ca3130. a biasing circuit provides two potentials for common use in the ?rst and second stages. terminal 8 can be used both for phase compensation and to strobe the out- put stage into quiescence. when terminal 8 is tied to the negative supply rail (terminal 4) by mechanical or electrical means, the output potential at terminal 6 essentially rises to the positive supply-rail potential at terminal 7. this condition of essentially zero current drain in the output stage under the strobed off condition can only be achieved when the ohmic load resistance presented to the ampli?er is very high (e.g.,when the ampli?er output is used to drive cmos digital circuits in comparator applications). input stage the circuit of the ca3130 is shown in the schematic diagram. it consists of a differential-input stage using pmos ?eld-effect transistors (q 6 , q 7 ) working into a mirror-pair of bipolar tran- sistors (q 9 , q 10 ) functioning as load resistors together with resistors r 3 through r 6 . the mirror-pair transistors also func- tion as a differential-to-single-ended converter to provide base drive to the second-stage bipolar transistor (q 11 ). offset null- ing, when desired, can be effected by connecting a 100,000 w potentiometer across terminals 1 and 5 and the potentiome- ter slider arm to terminal 4. cascade-connected pmos transistors q 2 , q 4 are the constant-current source for the input stage. the biasing circuit for the constant-current source is subsequently described. the small diodes d 5 through d 8 provide gate-oxide protection against high-voltage transients, including static electricity during handling for q 6 and q 7 . 3 2 1 8 4 6 7 q 1 q 2 q 4 d 1 d 2 d 3 d 4 q 3 q 5 d 5 d 6 d 7 d 8 q 9 q 10 q 6 q 7 5 z 1 8.3v input stage r 3 1k w r 4 1k w r 6 1k w r 5 1k w non-inv. input inv.-input + - r 1 40k w 5k w r 2 bias circuit current source for current source load for q 11 q 6 and q 7 v+ output output stage q 8 q 12 v- q 11 second stage offset null compensation strobing (note 5) note: 5. diodes d 5 through d 8 provide gate-oxide protection for mosfet input stage. ca3130, ca3130a
3-68 second-stage most of the voltage gain in the ca3130 is provided by the second ampli?er stage, consisting of bipolar transistor q 11 and its cascade-connected load resistance provided by pmos transistors q 3 and q 5 . the source of bias potentials for these pmos transistors is subsequently described. miller effect compensation (roll-off) is accomplished by simply connecting a small capacitor between terminals 1 and 8. a 47pf capacitor provides suf?cient compensation for stable unity-gain operation in most applications. bias-source circuit at total supply voltages, somewhat above 8.3v, resistor r 2 and zener diode z 1 serve to establish a voltage of 8.3v across the series-connected circuit, consisting of resistor r 1 , diodes d 1 through d 4 , and pmos transistor q 1 . a tap at the junction of resistor r 1 and diode d 4 provides a gate-bias potential of about 4.5v for pmos transistors q 4 and q 5 with respect to terminal 7. a potential of about 2.2v is developed across diode-connected pmos transistor q 1 with respect to terminal 7 to provide gate bias for pmos transistors q 2 and q 3 . it should be noted that q 1 is mirror-connected (see note 8) to both q 2 and q 3 . since transistors q 1 , q 2 , q 3 are designed to be identical, the approximately 200 m a current in q 1 estab- lishes a similar current in q 2 and q 3 as constant current sources for both the ?rst and second ampli?er stages, respec- tively. at total supply voltages somewhat less than 8.3v, zener diode z 1 becomes nonconductive and the potential, developed across series-connected r 1 , d 1 -d 4 , and q 1 , var- ies directly with variations in supply voltage. consequently, the gate bias for q 4 , q 5 and q 2 , q 3 varies in accordance with supply-voltage variations. this variation results in deterioration of the power-supply-rejection ratio (psrr) at total supply voltages below 8.3v. operation at total supply voltages below about 4.5v results in seriously degraded performance. output stage the output stage consists of a drain-loaded inverting ampli- ?er using cmos transistors operating in the class a mode. when operating into very high resistance loads, the output can be swung within millivolts of either supply rail. because the output stage is a drain-loaded ampli?er, its gain is dependent upon the load impedance. the transfer charac- teristics of the output stage for a load returned to the nega- tive supply rail are shown in figure 2. typical op amp loads are readily driven by the output stage. because large-signal excursions are non-linear, requiring feedback for good wave- form reproduction, transient delays may be encountered. as a voltage follower, the ampli?er can achieve 0.01% accuracy levels, including the negative supply rail. note: 8. for general information on the characteristics of cmos transis- tor-pairs in linear-circuit applications, see file number 619, data sheet on ca3600e cmos transistor array. input current variation with common mode input voltage as shown in the table of electrical speci?cations, the input current for the ca3130 series op amps is typically 5pa at t a = 25 o c when terminals 2 and 3 are at a common-mode potential of +7.5v with respect to negative supply terminal 4. figure 3 contains data showing the variation of input current as a function of common-mode input voltage at t a =25 o c. these data show that circuit designers can advantageously exploit these characteristics to design circuits which typically require an input current of less than 1pa, provided the com- mon-mode input voltage does not exceed 2v. as previously noted, the input current is essentially the result of the leakage current through the gate-protection diodes in the input circuit and, therefore, a function of the applied voltage. although the ?nite resistance of the glass terminal-to-case insulator of the 3 2 7 4 8 1 5 6 bias ckt. compensation (when required) a v ? 5x a v ? a v ? 6000x 30x input + - 200 m a 200 m a 1.35ma 8ma 0ma v+ output v- strobe c c offset null ca3130 (note 7) (note 5) notes: 6. total supply voltage (for indicated voltage gains) = 15v with input terminals biased so that terminal 6 potential is +7.5v above ter- minal 4. 7. total supply voltage (for indicated voltage gains) = 15v with out- put terminal driven to either supply rail. figure 1. block diagram of the ca3130 series 22.5 gate voltage (terminals 4 and 8) (v) output voltage (terminals 4 and 8) (v) 17.5 20 12.5 15 10 7.5 2.5 5 0 2.5 7.5 5 10 15 12.5 17.5 0 supply voltage: v+ = 15, v- = 0v t a = 25 o c load resistance = 5k w 500 w 1k w 2k w figure 2. voltage transfer characteristics of cmos output stage ca3130, ca3130a
3-69 metal can package also contributes an increment of leakage current, there are useful compensating factors. because the gate-protection network functions as if it is connected to ter- minal 4 potential, and the metal can case of the ca3130 is also internally tied to terminal 4, input terminal 3 is essen- tially guarded from spurious leakage currents. offset nulling offset-voltage nulling is usually accomplished with a 100,000 w potentiometer connected across terminals 1 and 5 and with the potentiometer slider arm connected to terminal 4. a ?ne offset-null adjustment usually can be effected with the slider arm positioned in the mid-point of the potentiometers total range. input-current variation with temperature the input current of the ca3130 series circuits is typically 5pa at 25 o c. the major portion of this input current is due to leakage current through the gate-protective diodes in the input circuit. as with any semiconductor-junction device, including op amps with a junction-fet input stage, the leakage current approximately doubles for every 10 o c increase in tempera- ture. figure 4 provides data on the typical variation of input bias current as a function of temperature in the ca3130. in applications requiring the lowest practical input current and incremental increases in current because of warm-up effects, it is suggested that an appropriate heat sink be used with the ca3130. in addition, when sinking or sourcing signi?cant output current the chip temperature increases, causing an increase in the input current. in such cases, heat- sinking can also very markedly reduce and stabilize input current variations. input offset voltage (v io ) variation with dc bias and device operating life it is well known that the characteristics of a mosfet device can change slightly when a dc gate-source bias potential is applied to the device for extended time periods. the magni- tude of the change is increased at high temperatures. users of the ca3130 should be alert to the possible impacts of this effect if the application of the device involves extended oper- ation at high temperatures with a signi?cant differential dc bias voltage applied across terminals 2 and 3. figure 5 shows typical data pertinent to shifts in offset voltage encountered with ca3130 devices (metal can package) dur- ing life testing. at lower temperatures (metal can and plas- tic), for example at 85 o c, this change in voltage is considerably less. in typical linear applications where the dif- ferential voltage is small and symmetrical, these incremental changes are of about the same magnitude as those encoun- tered in an operational ampli?er employing a bipolar transis- tor input stage. the 2v dc differential voltage example represents conditions when the ampli?er output stage is toggled, e.g., as in comparator applications. o 10 7.5 5 2.5 0 -101234567 input current (pa) input voltage (v) t a = 25 o c 3 2 7 4 8 6 pa v in ca3130 15v to 5v 0v to -10v v+ v- figure 3. input current vs common-mode voltage v s = 7.5v 4000 1000 100 10 1 -80 -60 -40 -20 0 20 40 60 80 100 120 140 input current (pa) temperature ( o c) figure 4. input current vs temperature figure 5. typical incremental offset-voltage shift vs operating life t a = 125 o c for to-5 packages 7 6 5 4 3 2 1 0 500 1000 1500 2000 2500 3000 3500 4000 offset voltage shift (mv) time (hours) differential dc voltage (across terminals 2 and 3) = 0v output voltage = v+ / 2 differential dc voltage (across terminals 2 and 3) = 2v output stage toggled 0 ca3130, ca3130a
3-70 power-supply considerations because the ca3130 is very useful in single-supply applica- tions, it is pertinent to review some considerations relating to power-supply current consumption under both single-and dual-supply service. figures 6a and 6b show the ca3130 connected for both dual-and single-supply operation. dual-supply operation: when the output voltage at terminal 6 is 0v, the currents supplied by the two power supplies are equal. when the gate terminals of q 8 and q 12 are driven increasingly positive with respect to ground, current ?ow through q 12 (from the negative supply) to the load is increased and current ?ow through q 8 (from the positive supply) decreases correspondingly. when the gate terminals of q 8 and q 12 are driven increasingly negative with respect to ground, current ?ow through q 8 is increased and current ?ow through q 12 is decreased accordingly. single-supply operation: initially, let it be assumed that the value of r l is very high (or disconnected), and that the input- terminal bias (terminals 2 and 3) is such that the output termi- nal (no. 6) voltage is at v+/2, i.e., the voltage drops across q 8 and q 12 are of equal magnitude. figure 20 shows typical qui- escent supply-current vs supply-voltage for the ca3130 oper- ated under these conditions. since the output stage is operating as a class a ampli?er, the supply-current will remain constant under dynamic operating conditions as long as the transistors are operated in the linear portion of their voltage-transfer characteristics (see figure 2). if either q 8 or q 12 are swung out of their linear regions toward cut-off (a non-linear region), there will be a corresponding reduction in supply-current. in the extreme case, e.g., with terminal 8 swung down to ground potential (or tied to ground), nmos transistor q 12 is completely cut off and the supply-current to series-connected transistors q 8 , q 12 goes essentially to zero. the two preceding stages in the ca3130, however, continue to draw modest supply-current (see the lower curve in figure 20) even though the output stage is strobed off. figure 6a shows a dual-supply arrangement for the output stage that can also be strobed off, assuming r l = by pulling the poten- tial of terminal 8 down to that of terminal 4. let it now be assumed that a load-resistance of nominal value (e.g., 2k w ) is connected between terminal 6 and ground in the circuit of figure 6b. let it be assumed again that the input-terminal bias (terminals 2 and 3) is such that the output terminal (no. 6) voltage is at v+/2. since pmos transistor q 8 must now supply quiescent current to both r l and transistor q 12 , it should be apparent that under these conditions the supply-current must increase as an inverse function of the r l magnitude. figure 22 shows the voltage- drop across pmos transistor q 8 as a function of load cur- rent at several supply voltages. figure 2 shows the voltage- transfer characteristics of the output stage for several values of load resistance. wideband noise from the standpoint of low-noise performance consider- ations, the use of the ca3130 is most advantageous in appli- cations where in the source resistance of the input signal is on the order of 1m w or more. in this case, the total input- referred noise voltage is typically only 23 m v when the test- circuit ampli?er of figure 7 is operated at a total supply volt- age of 15v. this value of total input-referred noise remains essentially constant, even though the value of source resis- tance is raised by an order of magnitude. this characteristic is due to the fact that reactance of the input capacitance becomes a signi?cant factor in shunting the source resis- tance. it should be noted, however, that for values of source resistance very much greater than 1m w , the total noise volt- age generated can be dominated by the thermal noise con- tributions of both the feedback and source resistors. figure 6a. dual power supply operation figure 6b. single power supply operation figure 6. ca3130 output stage in dual and single power supply operation 3 2 8 4 7 6 r l q 8 q 12 ca3130 + - v+ v- 3 2 8 4 7 6 r l q 8 q 12 ca3130 + - v+ 3 2 1 8 4 7 6 + - r s 1m w 47pf -7.5v 0.01 m f +7.5v 0.01 m f noise voltage output 30.1k w 1k w bw (-3db) = 200khz total noise voltage (referred to input) = 23 m v (typ) figure 7. test-circuit amplifier (30-db gain) used for wideband noise measurements ca3130, ca3130a
3-71 typical applications voltage followers operational ampli?ers with very high input resistances, like the ca3130, are particularly suited to service as voltage followers. figure 8 shows the circuit of a classical voltage fol- lower, together with pertinent waveforms using the ca3130 in a split-supply con?guration. a voltage follower, operated from a single supply, is shown in figure 9, together with related waveforms. this follower cir- cuit is linear over a wide dynamic range, as illustrated by the reproduction of the output waveform in figure 9a with input- signal ramping. the waveforms in figure 9b show that the follower does not lose its input-to-output phase-sense, even though the input is being swung 7.5v below ground poten- tial. this unique characteristic is an important attribute in both operational ampli?er and comparator applications. fig- ure 9b also shows the manner in which the cmos output stage permits the output signal to swing down to the nega- tive supply-rail potential (i.e., ground in the case shown). the digital-to-analog converter (dac) circuit, described later, illustrates the practical use of the ca3130 in a single-supply voltage-follower application. 9-bit cmos dac a typical circuit of a 9-bit digital-to-analog converter (dac) is shown in figure 10. this system combines the concepts of multiple-switch cmos lcs, a low-cost ladder network of dis- crete metal-oxide-?lm resistors, a ca3130 op amp con- nected as a follower, and an inexpensive monolithic regulator in a simple single power-supply arrangement. an additional feature of the dac is that it is readily interfaced with cmos input logic, e.g., 10v logic levels are used in the circuit of figure 10. the circuit uses an r/2r voltage-ladder network, with the output potential obtained directly by terminating the ladder arms at either the positive or the negative power-supply ter- minal. each cd4007a contains three inverters, each inverter functioning as a single-pole double-throw switch to terminate an arm of the r/2r network at either the positive or negative power-supply terminal. the resistor ladder is an assembly of 1% tolerance metal-oxide ?lm resistors. the ?ve arms requiring the highest accuracy are assembled with series and parallel combinations of 806,000 w resistors from the same manufacturing lot. a single 15v supply provides a positive bus for the ca3130 follower ampli?er and feeds the ca3085 voltage regulator. a scale-adjust function is provided by the regulator output control, set to a nominal 10v level in this system. the line- voltage regulation (approximately 0.2%) permits a 9-bit accuracy to be maintained with variations of several volts in the supply. the ?exibility afforded by the cmos building blocks simpli?es the design of dac systems tailored to par- ticular needs. single-supply, absolute-value, ideal full-wave recti?er the absolute-value circuit using the ca3130 is shown in figure 11. during positive excursions, the input signal is fed through the feedback network directly to the output. simultaneously, the positive excursion of the input signal also drives the output terminal (no. 6) of the inverting ampli?er in a negative-going excursion such that the 1n914 diode effectively disconnects the ampli?er from the signal path. during a negative-going excursion of the input signal, the ca3130 functions as a normal inverting ampli?er with a gain equal to -r 2 /r 1 . when the equality of the two equations shown in figure 11 is satis?ed, the full-wave output is symmetrical. peak detectors peak-detector circuits are easily implemented with the ca3130, as illustrated in figure 12 for both the peak-positive and the peak-negative circuit. it should be noted that with large-signal inputs, the bandwidth of the peak-negative cir- cuit is much less than that of the peak-positive circuit. the second stage of the ca3130 limits the bandwidth in this case. negative-going output-signal excursion requires a pos- itive-going signal excursion at the collector of transistor q 11 , which is loaded by the intrinsic capacitance of the associ- ated circuitry in this mode. on the other hand, during a neg- ative-going signal excursion at the collector of q 11 , the transistor functions in an active pull-down mode so that the intrinsic capacitance can be discharged more expeditiously. ca3130, ca3130a
3-72 3 2 1 8 4 7 6 + - 10k w c c = 56pf -7.5v 0.01 m f +7.5v 0.01 m f 2k w 2k w bw (-3db) = 4mhz sr = 10v/ m s 25pf 0.1 m f top trace: output center trace: input figure 8a. small-signal response (50mv/div., 200ns/div.) top trace: output signal; 2v/div., 5 m s/div. center trace: difference signa; 5mv/div., 5 m s/div. bottom trace: input signal; 2v/div., 5 m s/div. figure 8b. input-output difference signal showing settling time (measurement made with tektronix 7a13 differential amplifier) figure 8. split supply voltage follower with associated waveforms 3 2 8 1 4 7 6 + - 10k w 56pf offset +15v 0.01 m f 2k w 0.1 m f 5 adjust 100k w figure 9a. output waveform with input signal ramping (2v/div., 500 m s/div.) top trace:output; 5v/div., 200 m s/div. bottom trace:input signal; 5v/div., 200 m s/div. figure 9b. output waveform with ground reference sine-wave input figure 9. single supply voltage follower with associated waveforms. (e.g., for use in single-supply d/a converter; see figure 9 in an6080) ca3130, ca3130a
3-73 figure 10. 9-bit dac using cmos digital switches and ca3130 figure 11. single supply, absolute value, ideal full-wave rectifier with associated waveforms 6 3 10 10 3 6 4 8 3 6 7 9 4 10 2 3 13 8 12 12 1 5 8 13 13 1 12 8 5 14 11 2 6 5 1 7 7 1 6 8 4 3 2 10v logic inputs +10.010v lsb 987 654 321 msb 806k 1% paralleled resistors +15v voltage follower ca3130 output load 100k offset null 56pf 2k 0.1 m f regulated voltage adj 22.1k 1% 1k 3.83k 1% 0.001 m f ca3085 voltage regulator +15v 2 m f 25v + - +10.010v cd4007a switches cd4007a switches 402k 1% 200k 1% 100k 1% 806k 1% 806k 1% 806k 1% 750k 1% 806k 1% 806k 1% 806k 1% 806k 1% (2) (4) (8) 806k 1% + - 62 bit 1 2 3 4 5 6 - 9 required ra tio-ma tch standard 0.1% 0.2% 0.4% 0.8% 1% abs note: all resistances are in ohms. cd4007a switches 1 5 10k 2 3 4 6 8 1 5 7 r 2 2k w +15v 0.01 m f 1n914 r 3 5.1k w peak adjust 2k w 100k w offset adjust 20pf ca3130 r 1 4k w + - 20v p-p input: bw(-3db) = 230khz, dc output (avg) = 3.2v 1v p-p input: bw(-3db) = 130khz, dc output (avg) = 160mv gain = r 2 r 1 ------ - = x = r 3 r 1 +r 2 +r 3 ------------------------------------- - r 3 =r 1 x+x 2 1 - x ------------------ ? ?? for x = 0.5: 2k w 4k w ----------- - = r 2 r 1 ------ - r 3 = 4k w 0.75 0.5 ----------- ? ?? = 6k w top trace: output signal; 2v/div. bottom trace: input signal; 10v/div. time base on both traces: 0.2ms/div. 0v 0v ca3130, ca3130a
3-74 figure 12a. peak positive detector circuit figure 12b. peak negative detector circuit figure 12. peak-detector circuits figure 13. voltage regulator circuit (0v to 13v at 40ma) 3 2 6 4 7 ca3130 +7.5v 0.01 m f +dc output 5 m f + - 100 k w 1n914 0.01 m f -7.5v 2k w 10k w + - 6v p-p input; bw (-3db) = 1.3mhz 0.3v p-p input; bw (-3db) = 240khz 3 2 6 4 7 ca3130 +7.5v 0.01 m f -dc output 5 m f + - 100 k w 1n914 0.01 m f -7.5v 2k w 10k w + - 6v p-p input; bw (-3db) = 360khz 0.3v p-p input; bw (-3db) = 320khz 6 3 2 1 8 7 4 ca3086 current limit adj 3 w r 2 1k w q 5 13 14 12 q 1 q 2 q 3 q 4 10 7 3 4 2 6 9 11815 390 w 1k w 20k w + - 5 m f 25v 56pf error amplifier ca3130 30k w 100k w ic1 0.01 voltage adjust 50k w r 1 14 13 q 5 12 62k w ic 3 output 0 to 13v at 40ma + - 0.01 m f +20v input 2.2k w + - 25 m f ic 2 ca3086 10 11 1, 2 q 4 q 1 8, 7 5 q 3 q 2 6 4 regulation (no load to full load): <0.01% input regulation: 0.02%/v hum and noise output: <25 m v up to 100khz + - + - 1k w 9 m f 3 ca3130, ca3130a
3-75 error-ampli?er in regulated-power supplies the ca3130 is an ideal choice for error-ampli?er service in regulated power supplies since it can function as an error- ampli?er when the regulated output voltage is required to approach zero. figure 13 shows the schematic diagram of a 40ma power supply capable of providing regulated output voltage by continuous adjustment over the range from 0v to 13v. q 3 and q 4 in lc 2 (a ca3086 transistor-array lc) func- tion as zeners to provide supply-voltage for the ca3130 comparator (ic 1 ). q 1 , q 2 , and q 5 in ic 2 are con?gured as a low impedance, temperature-compensated source of adjust- able reference voltage for the error ampli?er. transistors q 1 , q 2 , q 3 , and q 4 in lc 3 (another ca3086 transistor-array lc) are connected in parallel as the series-pass element. tran- sistor q 5 in lc 3 functions as a current-limiting device by diverting base drive from the series-pass transistors, in accordance with the adjustment of resistor r 2 . figure 14 contains the schematic diagram of a regulated power-supply capable of providing regulated output voltage by continuous adjustment over the range from 0.1v to 50v and currents up to 1a. the error ampli?er (lc 1 ) and circuitry associated with lc 2 function as previously described, although the output of lc 1 is boosted by a discrete transistor (q 4 ) to provide adequate base drive for the darlington-con- nected series-pass transistors q 1 , q 2 . transistor q 3 func- tions in the previously described current-limiting circuit. multivibrators the exceptionally high input resistance presented by the ca3130 is an attractive feature for multivibrator circuit design because it permits the use of timing circuits with high r/c ratios. the circuit diagram of a pulse generator (astable multivibrator), with provisions for independent control of the on and off periods, is shown in figure 15. resistors r 1 and r 2 are used to bias the ca3130 to the mid-point of the supply-voltage and r 3 is the feedback resistor. the pulse repetition rate is selected by positioning s 1 to the desired position and the rate remains essentially constant when the resistors which determine on-period and off-period are adjusted. function generator figure 16 contains a schematic diagram of a function genera- tor using the ca3130 in the integrator and threshold detector functions. this circuit generates a triangular or square-wave output that can be swept over a 1,000,000:1 range (0.1hz to 100khz) by means of a single control, r 1 . a voltage-control input is also available for remote sweep-control. the heart of the frequency-determining system is an opera- tional-transconductance-ampli?er (ota) (see note 10), lc 1 , operated as a voltage-controlled current-source. the output, i o , is a current applied directly to the integrating capacitor, c 1 , in the feedback loop of the integrator lc 2 , using a ca3130, to provide the triangular-wave output. potentiometer r 2 is used figure 14. voltage regulator circuit (0.1v to 50v at 1a) 6 2 3 1 8 7 4 4.3k w 1 w + - 43k w 100 m f error amplifier ic 1 voltage adjust 14 13 100 m f +55v input 2.2k w + - ic 2 ca3086 10, 11 q 4 q 1 q 2 6 regulation (no load to full load): <0.005% input regulation: 0.01%/v hum and noise output: <250 m v rms up to 100khz + - + - ca3130 + - + - 1w 3.3k w 1w 5 m f 9 8, 7 q 3 1, 2 3 5 4 1k w 62k w q 5 12 10k w q 2 q 1 50k w q 3 1k w 2n3055 2n2102 current limit adjust 2n5294 2n2102 q 4 1000pf 10k w 8.2k w output: 0.1 to 50v at 1a ca3130, ca3130a
3-76 to adjust the circuit for slope symmetry of positive-going and negative-going signal excursions. another ca3130, ic 3 , is used as a controlled switch to set the excursion limits of the triangular output from the integra- tor circuit. capacitor c 2 is a peaking adjustment to opti- mize the high-frequency square-wave performance of the circuit. potentiometer r 3 is adjustable to perfect the amplitude symmetry of the square-wave output signals. output from the threshold detector is fed back via resistor r 4 to the input of lc 1 so as to toggle the current source from plus to minus in generating the linear triangular wave. operation with output-stage power-booster the current-sourcing and-sinking capability of the ca3130 output stage is easily supplemented to provide power-boost capability. in the circuit of figure 17, three cmos transistor- pairs in a single ca3600e (see note 12) lc array are shown parallel connected with the output stage in the ca3130. in the class a mode of ca3600e shown, a typical device con- sumes 20ma of supply current at 15v operation. this arrangement boosts the current-handling capability of the ca3130 output stage by about 2.5x. the ampli?er circuit in figure 17 employs feedback to estab- lish a closed-loop gain of 48db. the typical large-signal bandwidth (-3db) is 50khz. note: 9. see file number 619 for technical information. 7 4 6 3 2 r 1 100k w r 2 100k w r 3 100k w on-period adjust 1m w 2k w 2k w off-period adjust 1m w +15v 0.01 m f output 2k w 0.001 m f 0.01 m f 0.1 m f 1 m f s 1 ca3130 + - figure 15. pulse generator (astable multivibrator) with provisions for independent control of on and off periods frequency range: position of s 1 0.001 m f 0.01 m f 0.1 m f 1 m f pulse period 4 m s to 1ms 40 m s to 10ms 0.4ms to 100ms 4ms to 1s note: 10. see ?le number 475 and an6668 for technical information. figure 16. function generator (frequency can be varied 1,000,000/1 with a single control) 6 3 2 1 4 7 5 6 2 3 4 7 8 1 5 4 6 7 3 2 r 4 270k w +7.5v voltage-controlled current source ic 1 3k w 3k w 10m w +7.5v r 2 100k w slope symmetry adjust voltage controlled input -7.5v 10k w 10k w r 1 -7.5v frequency adjust (100khz max) -7.5v +7.5v i o ic 2 +7.5v c 1 100pf integrator -7.5v 56pf ca3130 + - ca3080a + - 39k w 3 - 30pf c 2 adjust high - freq. detector threshold 150k w ic 3 +7.5v ca3130 + - r 3 100k w amplitude symmetry adjust 22k w -7.5v (note 10) ca3130, ca3130a
3-77 notes: 11. transistors q p1 , q p2 , q p3 and q n1 , q n2 , q n3 are parallel connected with q 8 and q 12 , respectively, of the ca3130. 12. see file number 619. figure 17. cmos transistor array (ca3600e) connected as power booster in the output stage of the ca3130 8 7 3 2 +15v 2k w ca3130 + - 4 10 3 6 4 9 7 6 14 750k w 1 m f 2 11 13 1 12 5 8 1 m f 1m w 0.01 m f 510k w 500 m f q p3 q n1 q n2 q n3 q p2 q p1 ca3600e a v(cl) = 48db large signal bw (-3 db) = 50khz r l = 100 w (p o = 150mw at thd = 10%) (note 12) input typical performance curves figure 18. open loop gain vs temperature figure 19. open-loop response load resistance = 2k w 150 140 130 120 110 100 90 80 -100 -50 0 50 100 open loop voltage gain (db) temperature ( o c) supply voltage: v+ = 15v; v- = 0 t a = 25 o c f ol 3 2 1 1 2 3 4 4 aol 1 - c l = 9pf, c c = 0pf, r l = 2 - c l = 30pf, c c = 15pf, r l = 2k w 3 - c l = 30pf, c c = 47pf, r l = 2k w 4 - c l = 30pf, c c = 150pf, r l = 2k w 120 100 80 60 40 20 0 open loop voltage gain (db) -100 -200 -300 open loop phase (degrees) 10 2 10 3 10 4 10 5 10 6 10 7 10 8 frequency (hz) 10 1 ca3130, ca3130a
3-78 all harris semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. harris semiconductor products are sold by description only. harris semiconductor reserves the right to make changes in circuit design and/or speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by harris is believed to be accurate and reliable. however, no responsibility is assumed by harris or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of harris or its subsidiaries. sales of?ce headquarters for general information regarding harris semiconductor and its products, call 1-800-4-harris north america harris semiconductor p. o. box 883, mail stop 53-210 melbourne, fl 32902 tel: 1-800-442-7747 (407) 729-4984 fax: (407) 729-5321 europe harris semiconductor mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia harris semiconductor pte ltd. no. 1 tannery road cencon 1, #09-01 singapore 1334 tel: (65) 748-4200 fax: (65) 748-0400 semiconductor figure 20. quiescent supply current vs supply voltage figure 21. quiescent supply current vs supply voltage figure 22. voltage across pmos output transistor (q 8 ) vs load current figure 23. voltage across nmos output transistor (q 12 ) vs load current typical performance curves (continued) load resistance = t a = 25 o c v- = 0 output voltage balanced = v+/2 output voltage high = v+ or low = v- 17.5 12.5 10 7.5 5 2.5 0 6 8 10 12 14 16 18 total supply voltage (v) quiescent supply current (ma) 4 output voltage = v+/2 v- = 0 14 12 10 8 6 4 2 0246 810121416 quiescent supply current (ma) total supply voltage (v) t a = -55 o c 25 o c 125 o c 0 50 10 1 0.1 0.01 0.001 0.001 0.01 0.1 1.0 10 100 magnitude of load current (ma) voltage drop across pmos output stage transistor (v) 15v 10v negative supply voltage = 0v t a = 25 o c positive supply voltage = 5v negative supply voltage = 0v t a = 25 o c 50 10 1 0.1 0.01 0.001 0.001 0.01 0.1 1 10 100 magnitude of load current (ma) voltage drop across nmos output stage transistor (v) 15v 10v positive supply voltage = 5v ca3130, ca3130a

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